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Showing posts from February, 2020

AArch64/x86_64 quiz & Lab 4 Info/Update

This post is going to serve as an info dump for the previous few weeks in class. I've had a pair of WIP posts for the AArch64/x86_64 quiz and Lab 4 sitting in my drafts, so i've decided to merge them. The AArch64/x86_64 quiz went very well. Prior to the quiz, I met with some of my peers for a study session regarding the previous week's material. While the x86_64 architecture is significantly more confusing than the AArch64 architecture, both architectures have similar functionality i.e. accessing registers in 8, 16, 32, 64 bits, safe registers to avoid trampling, and specifying which register to store results. Outside of the architecture material, we also spent some time reviewing bit-flipping with XOR(EOR). Even though it was not on the quiz, I greatly enjoyed this topic. Working with logic gates was my gateway to programming, and using the exclusive-or gate to flip bits was an interesting miniature logic puzzle. I'm hoping to have XOR/EOR appear on a quiz later in t